Analog-to-digital sigma-delta converters of different topologies have been devised and described in numerous publications. Most of the studies focus on single-loop topologies either with single or multi-bit quantizers, the filter transfer function of which ranges from the second to the fifth order.
In voice and audio applications, sigma-delta converters may be classified as a sigma-delta converter of up to the second order, or a sigma-delta converter of order greater than 2.
For sigma-delta converters of up to the second order, they are hardly used in audio applications because of the presence of idle tones due to pattern noise for low DC voltages. Moreover, they require a large over-sampling factor (OSF>128).
For sigma-delta converters of order greater than 2, they are often used in high fidelity audio applications for high signal-to-noise ratio values. It is rather difficult to make them stable because of the non-linearity that is intrinsically present in the loop. A large signal-to-noise ratio (SNR), a low OSF and low idle tones are peculiar features of these converters.
The article by R. W. Adams et al., “Theory and Practical Implementation of a Fifth-Order Sigma-Delta A/D Converter”, J. Audio Eng. Soc., Vol. 39, No. 7/8, July/August 1991, discloses a converter with an 18-bit, fifth order, simple-sampled, single-loop, inverse Chebyshev filter topology plus an integrator reset. The main features of this architecture are a fifth order converter, a high signal-to-noise ratio, and a relatively small over-sampling factor.
Unfortunately, this type of converter is burdened with the following drawbacks. It is not a double-sampled architecture. Consequently, there is a very high current consumption because the sampling frequency is twice that needed in a double-sampled architecture. Moreover, the operational amplifiers of the converter need to be designed accurately because they need to have a wide operating frequency band.
Other drawbacks are that the converter is not intrinsically stable. As a result, stability needs to be ensured by an external resetting of the floating nodes of the circuit. The converter also needs external digital circuitry to reset the floating nodes. As a result, there is an increase of silicon area occupation and in the design complexity.
A basic scheme of a multi-bit sigma-delta converter and a detailed circuit architecture of another second-order double-sampled sigma-delta converter for audio applications, as disclosed in European patent application EP 901,233, are depicted in FIGS. 1 and 2. The European patent application is assigned to the current assignee of the present invention, and is hereby incorporated by reference in its entirety.
Different from the scheme of FIG. 1, the sigma-delta converter of FIG. 2 does not have a multi-bit (N) quantizer (Q). However, it does have a comparator and a D-type flip-flop, which is practically a one-bit quantizer. The switched-capacitor structures are controlled by control signals, the active phases of which are non-overlapping.
This type of converter has the following advantages. It is suitable for audio or simple RF (radio-frequency) applications. It has a limited current consumption because of the double sampling approach, and is fully floating. Thus, there is no in-band folding of high frequency noise due to a mismatch. Unfortunately, a second order single bit topology is unsuitable for most RF applications because of a low signal-to-noise ratio with a broad input frequency band (2 MHz for the WCDMA standard).
Another converter is disclosed in the paper by C. Pinna et al., “A CMOS 64 MSps 20 mA 0.85 mm2 Baseband I/Q Modulator Performing 13 bits over 2 MHz Bandwidth”. It is based on a 211 Mash architecture and is depicted in FIGS. 3 and 4. This converter has a first two-stage loop that generates the digital signal Y1 and two single-stage loops that generate the signals Y2 and Y3.
The converter has good performance at the cost of an accurate design and realization of dedicated digital blocks to process intermediate signals, and to provide the required synchronization. The output Y is generated by combining the output Y1 of a multi-bit quantizer with the outputs Y2 and Y3 from the two auxiliary blocks of the single-stage loops. The study of stability is greatly simplified because of the multi-bit quantizer, and more accurately approaches the ideal linear behavior. In contrast, the Adams et al. converter does not have a multi-bit quantizer, and stability is a more difficult task.
Of course, multi-loop topologies ensure stability, but they need to be properly designed and the loops need to be accurately synchronized.
Another advantage of using a multi-bit quantizer includes a wider dynamic input range of the converter than in similar topologies that use a single-bit quantizer. However, this converter is relatively sensitive to capacitor mismatches and to nonlinearities of the operational amplifiers. This is a significant drawback in audio applications and in high performance cellular phones where a high SNR is required.